C8051F380/1/2/3/4/5/6/7/C
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
1
0
Name
ENSMB0
INH0
BUSY0
EXTHOLD0 SMB0TOE SMB0FTE
SMB0CS[1:0]
Type
R/W
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC1; SFR Page = 0
Bit Name
Function
7
6
5
4
3
2
ENSMB0
INH0
BUSY0
EXTHOLD0
SMB0TOE
SMB0FTE
SMBus0 Enable.
This bit enables the SMBus0 interface when set to 1. When enabled, the interface
constantly monitors the SDA0 and SCL0 pins.
SMBus0 Slave Inhibit.
When this bit is set to logic 1, the SMBus0 does not generate an interrupt when
slave events occur. This effectively removes the SMBus0 slave from the bus. Mas-
ter Mode interrupts are not affected.
SMBus0 Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free-timeout is sensed.
SMBus0 Setup and Hold Time Extension Enable.
This bit controls the SDA0 setup and hold times according to Table 22.2.
0: SDA0 Extended Setup and Hold Times disabled.
1: SDA0 Extended Setup and Hold Times enabled.
SMBus0 SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus0 forces
Timer 3 to reload while SCL0 is high and allows Timer 3 to count when SCL0 goes
low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in
reload while SCL0 is high. Timer 3 should be programmed to generate interrupts at
25 ms, and the Timer 3 interrupt service routine should reset SMBus0 communica-
tion.
SMBus0 Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL0 and SDA0
remain high for more than 10 SMBus clock source periods.
1:0 SMB0CS[1:0] SMBus0 Clock Source Selection.
These two bits select the SMBus0 clock source, which is used to generate the
SMBus0 bit rate. The selected device should be configured according to
Equation 22.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
Rev. 1.4
211
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